Recent NAND-type flash memory has a single-level cell (SLC) capable of storing one bit (bit) in a memory device and a multi-level cell (MLC) capable of storing two bits or more in a memory device. The feature of a memory device of NAND-type flash memory is that stored data is not erased even if the power is switched off; however, there is generally a limit in the number of rewrites of a memory device, and if the number of rewrites exceeds a specified number, the possibility of causing a malfunction in a write and an erase operation is increased.
If a specific memory cell (or area) is repeatedly rewritten and exceeds the above limit, the target area may malfunction. However, if the whole memory device area is evenly rewritten, it is possible to prevent the number of rewrites of specific memory cells (or areas) from increasing suddenly. As a result, it causes an increase in total rewrite capacity as the whole NAND-type flash memory. The total rewrite capacity here indicates one obtained by multiplying written capacity by the number of rewrites.
SLC can keep a wide margin in distribution between threshold values corresponding to each data compared with MLC. Hence, it is said that an upper limit to the number of rewrites is comparatively large, and SLC is more suitable for use with the large number of rewrites. However, MLC can realize severalfold memory capacity per single device compared with SLC. Therefore, the cost per bit becomes cheaper, and MLC is very advantageous in terms of cost benefits.
For the purpose of making use of the above-mentioned merits and demerits of both SLC and MLC, an SLC area and an MLC area may be used while divided in a memory device area of NAND-type flash memory. A method for leveling the numbers of rewrites in both of the SLC area and the MLC area is devised in such a product.